1. Field of the Invention
The present invention relates to fast and robust apparatus used for wireless communication systems, such as but not limited to wireless local area networks (WLAN), and in particular to a fast and robust apparatus having an automatic gain control (AGC) gain setting.
2. Background
The present invention relates to wireless communication systems, such as but not limited to wireless local area networks (WLAN), and in particular to an 802.11a/b/g/n receiver base-band modem that provides a fast and robust automatic gain control (AGC) function for various RF transceiver ICs. In a typical WLAN environment, the received signal strength can vary with a dynamic range up to 100 dB depending on the distance between a transmitter and a receiver. An Automatic Gain Control (AGC) circuitry has been widely used in WLAN receivers to optimize its range performance.
While implemented, a typical WLAN transceiver consists of three chips, one power amplifier (PA) chip, one RF transceiver chip, and one integrated base-band (BB) and Medium Access Control (MAC) chip. To further lower down the total cost of a WLAN transceiver, integration of the PA chip into the RF transceiver chip has been achieved. Development effort in accomplishing a single-chip WLAN transceiver implementation has also been announced. FIG. 1 shows a functional block diagram for a wireless transceiver, which includes a direct-conversion (also known as zero-IF) receiver, for WLAN applications. At the highest level, it contains four functional blocks: an antenna 11, an antenna switch 12, a transmitter 20 and a receiver 10. While transmitting, the antenna switch position is such that a transmitter is connected to the antenna and the RF receiver is normally turned off to save power. While receiving, the antenna switch is positioned such that the RF receiver is connected to the antenna, and the transmitter is normally turned off. For all the discussions below, one can assume that the transceiver is in the receiving mode and the transmitter is turned off.
As is shown in FIG. 1, a typical zero-IF receiver 10 consists of a Low Noise Amplifier (LNA) 13, a pair of mixer 14a and 14b, a pair of channel selection filter 17a and 17b, and a pair of multiple stages of Variable Gain Amplifiers (VGA's) 18a and 18b. The LNA 13 is used to amplify a weak received signal with minimum distortion. In other words, the LNA Block 13 is used to enhance the sensitivity of the receiver. To provide the best sensitivity, a LNA stage provides a gain about 15 dB with a noise figure (NF) between 1.5 to 2.5 dB. Multiple stages of LNA's can be used to further enhance the receiver sensitivity in the presence of a weak received signal.
In the presence of a very strong signal, it is usually desirable to turn off some or all stages of the LNA's if multiple LNA's are used. The output of the LNA 13 is connected to a pair of mixers 14a and 14b. To keep the fidelity of the received signal, two mixers are required to provide an in-phase and a quadrature phase base-band signals. One mixer 14a, which takes the carrier generated by the synthesizer 16 as one input and the LNA 13 output as another input, converts the received Radio Frequency (RF) signal to a base-band in-phase signal (also known as I-channel) as its output. While the other mixer 14b, which uses a 90-degree phase-shifted carrier 15 as one input and the LNA 13 output as another input, to convert the received RF signal to a baseband quadrature-phase signal (also known as Q-channel) as its output. In what follows, the received in-phase and quadrature signals will be referred as I-channel and Q-channel signals, respectively. From now on, the processing of both I-channel and Q-channel signals is essentially the same. So it is sufficient to describe the processing of the I-channel signal.
For the I-channel signal, a low-pass Filter 17a is applied to the corresponding mixer output to filter out the adjacent channel interferences and the unwanted mixer output at twice the RF signal frequency. The I-channel filter output is connected to the Variable Gain Amplifiers (VGA) 18a for gain adjustment. In this diagram, each VGA 18a contains two Variable Gain Amplifier stages 19a and 19b) with their gain controlled by the AGC control signals (as shown in FIG. 1) generated by AGC 22. A designer may use 3 or more VGA stages to implement the VGA function 18a. As its name shows, each VGA stage 19a or 19b allows one to adjust its control voltage for providing variable gain to its input signal. The output of the VGA 18a is connected to an analog-to-digital converter (ADC) 21a of the base-band modem 40. The ADC 21a digitizes and coverts an input signal to the signed ADC samples from 210a to facilitate further processing of the received signal by the base-band demodulator processor 23 in digital domain. Detail operations will be presented later.
To fully utilize the dynamic range of an ADC, the input to an ADC needs to be maintained at or close to an optimal level. This is achieved by the AGC circuitry 22. The AGC circuitry, most commonly implemented in the base-band demodulator receiver 40, estimates the received signal strength and then properly adjusts the modes of the LNA 13 and the gains of the VGA's 18a and 18b in the RF receiver. The MUX 2220 is used to select a digital or analog AGC control signal according to its RF Receiver 30. If the AGC gain is controlled by an analog signal, a digital-to-analog converter (DAC) 2210 is required to convert the digital AGC control signal to the correspondent analog control signal.
For an 802.11a/b/g/n receiver to achieve optimal performance, this function needs to be accomplished in about 2 micro-seconds. This requirement makes the AGC function a challenge with a received signal strength variation of up to 100 dB.
More details on the AGC function will be presented below. To properly support the AGC function, one can use multiple stages of VGA's 18a and 18b. The total gain of the VGA's is usually controlled by the AGC 22 in the base-band demodulator 40. Dependent on its control voltage, a typical VGA stage can provide a gain from 0 dB to around 25 dB. With two to three stages of VGA's, a total received signal dynamic range around 75 dB can be supported. This is insufficient to support a dynamic range of up to 100 dB. Therefore, some RF transceivers provide either (1) means for switching off its low noise amplifier (LNA) and/or an intentional mis-matched antenna switch connection or (2) multiple switch-able stages of LNA's to extend the receive signal dynamic range further.
For IEEE 802.11g or 802.11n WLAN application, it is required to detect the signal presence and determine the signal strength (for AGC to settle close to its final gain), and turn on or off the LNA stages (or, equivalently in a two-stage LNA design, set the LNA gain to maximum by turning on both LNA stages, medium by turning off one LNA stage, or minimum by turning off both LNA stages) as necessary, all within about 2 micro-seconds. Hence, the implementation of the AGC circuitry becomes even more critical to an 802.11b, 802.11g, 802.11a, or 802.11n WLAN receiver.
For a detailed discussion, a traditional AGC 22 is shown in FIG. 2. Since the ADC digitizes the received analog waveform and provides unsigned integers as outputs, the paired ADC outputs from both channels are coupled into a pair of Converters 210a and 201b. The signed ADC output samples are obtained in 210a and 210b by subtracting the middle value of an N-bit ADC's dynamic range from the unsigned ADC output samples. After the paired Converters, the signed outputs of the i-th received samples (which are denoted as Ii and Qi) are coupled into the Power Detector 224. The measured power (Pi) of the i-th paired samples is then compared with the desired digitized signal power (PD). PD is typically chosen such that the full dynamic range of the ADC can be used. The multiplier 222 is used to control the AGC loop gain, which has an adjustable gain, k. The accumulator 228 uses an adder 228a and a delay 228b to track the history of accumulated AGC power error. The accumulator 228 output is an appropriate digital gain value, linear. Since VGA and LNA gains are typically adjusted in dB while the digital value Giinear is evaluated in “linear” domain, a VGA/LNA gain mapping 223 typically takes the digital value linear and converts into to proper LNA and VGA gain control signals.
One may measure and average more pair of I/Q samples before the subtractor 226 for a better power measurement in statistics. However, the more samples are measured, the slower the AGC gain is adjusted. The other drawback of this AGC operation is from the saturated samples. In order to be able to receive the smallest signal, the AGC 22 is initially set to have the maximum gain when no signal was present (noise only). For a better explanation, a few I or Q waveforms, when the ADC is allowed to have unlimited number of bits, after the Converters 210a and 210b are shown in FIG. 3. Two dashed horizontal lines show the levels at which the waveform samples would have been clipped for an N-bit ADC. When a waveform sample was clipped, an N-bit ADC was called “saturated” below. For a pair of N-bit ADCs, the dynamic signal range (in dB) is proportional to the bit-number, N. However, the greater N is, the higher cost is to build this pair of ADCs. For a practical WLAN system, the bit number N used is much smaller than its signal dynamic range (around 100 dB). Therefore, the dynamic range of an incoming signal (depending upon the distance between a transmitter and the receiver) may be 30 dB or greater in power than that of a pair of N-bit ADCs. With the AGC gain set at maximum while waiting for a WLAN signal, the presence of a WLAN signal will typically cause most or all N-bit ADC outputs being saturated, as shown in FIG. 3a and FIG. 3b. For explanation simplicity, it is assumed that the number of ADC output saturations in Cases A and B is similar. Since a pair of saturated ADC output does not provide the information as to how big the input signal power is compared to the maximal ADC dynamic range, the estimated AGC power errors are insufficient for the AGC block to determine the correct AGC gain, which should be a few dB lower in Case A, and quite a few dB lower in Case B. A greater reduction in AGC gain is desirable for Case B, while the same gain reduction would have caused the received signal to be too small at the output of the ADC for Case A.
When AGC sometimes over-reacts, it can cause the digitized samples to be much smaller such as shown in FIG. 3c and FIG. 3d. The conventional AGC algorithm applied for these cases can be explained as follows. For a faster convergence, a higher loop gain 222 can cause AGC gain oscillation and the AGC loop may become unstable. On the other hand, a smaller loop gain 222 will take a significant time for the AGC block to converge to the desired AGC gain. Intuitively, one may count the statistics of the saturation of ADC outputs to aid the AGC block. In cases of FIG. 3c and FIG. 3d, if one counts not only the saturations of the ADC outputs but also the “saturations” of several other power levels as shown in FIG. 3c and FIG. 3d, a better estimate of received signal power can be obtained.
A traditional AGC loop (without saturation-detection aided algorithm) as shown in FIG. 2 requires significant time for AGC gain to converge and hence is not suitable for applications like WLAN. Typically, the loop gain is set to be small for a slow but smooth AGC gain convergence. The power error of ADC output samples are averaged for a sufficient time for a better power estimate in statistics. When a higher AGC gain is used for a fast converge AGC loop, the AGC gain may be oscillating too much and the system performance is degraded. A slow convergence AGC loop is not suitable for a system requires AGC gain to converge within a few micro-seconds, e.g., a WLAN packet with very short preambles (or short training sequence). The aided algorithm should be used to shorten the AGC convergence time.
A traditional saturation-detection aided AGC algorithm uses the saturated ADC samples only, i.e., 0 and 2N−1 for an N-bit ADC. However, a 802.11a/g/n WLAN signal uses OFDM modulation which can have a peak-to-average power ratio around 10 dB. For such a modulated signal, a back-off of more than 6 dB is typically required so the signal is not clipped (distorted) going through the ADC. In this case, the ADC saturation in statistics is a rare event and it is not a useful indication to determine if the AGC gain is too high or not. In addition, the ADC saturation indicates the AGC gain may be too high but there is no aided algorithm for the cases when the AGC gain is too low. Therefore, it is faster and easier to adjust the AGC from high gain to low gain than to adjust the AGC from low gain to high gain for a traditional saturation-detection aided algorithm. Furthermore, a traditional Receive Signal Strength Indicator (RSSI) aided AGC algorithm requires significant time for an accurate RSSI estimate; a drawback for a WLAN system which requires a quick and fast AGC convergence. In addition, a long RSSI measurement time results in a slow AGC gain adjustment, and hence less time remains for a traditional AGC loop (FIG. 2) which is slow but precise in gain convergence, a desirable property for AGC gain fine-tuning Furthermore, since a lock-up time (with fixed AGC gain) is required for an accurate RSSI measurement, this lock-up time can cause the loss of a WLAN packet with a very short preamble or training sequence, in case the receiver gets into a false alarm mode immediately before the arrival the packet.
This invention application is focused on the AGC 22 which is part of the receiver function. The overall amplifier gain provided by a receiver (including LNAs and VGAs) is denoted as “AGC gain” in this application. In general, the higher the received signal power, the smaller the AGC gain is provided by the receiver. The AGC 22 is used to measure the received signal power and apply an appropriate AGC gain (by changing LNA on/off states and/or VGA gains) so the received signal is appropriately amplified and the outputs of VGAs 18 can fully utilize the designed dynamic range of an ADC. If the AGC gain is too high, the ADC will be saturated and the ADC output signal is distorted. If the AGC gain is too small, the ADC outputs are too small (a waste of the ADC's dynamic range), which can cause the baseband demodulator processor to decode the data incorrectly. In summary, the system performance will be degraded in both cases. In practice, the AGC function needs to correctly estimate the received signal power of a wideband 802.11a/b/g/n signal within a few micro-seconds by adjusting the VGA gains and, if needed, switching off one or more LNA stages which has a settling time of a couple hundreds of nano-seconds each to achieve a receiver dynamic range around 100 dB. To implement a fast-and-precise AGC algorithm in a few micro-seconds for a receive signal with a 100 dB dynamic range is a great challenge for any WLAN receiver. Therefore, the purpose of this invention application is to provide a few simple-fast-and-reliable aided AGC algorithms for AGC 22 during coarse and fine AGC tunings.
This invention presents an innovative statistics-aided AGC algorithm based on the statistics of the ADC outputs. The benefit of using this digital AGC algorithm is multifold: (1) it provides a simple aided algorithm to be appended to a traditional AGC block 22, (2) it provides a faster and more robust AGC convergence than a tradition aided AGC algorithm, and (3) it provides a generic algorithm that can be applied to the front-end of various RF receivers, which typically are required to detect a signal with up to 100 dB power variations.
U.S. Pat. No. 7,936,850, issued to Eric Rodal et al. entitled “Method and apparatus for providing a digital automatic gain control (AGC)” discloses a logarithmic analog-to-digital converter for sampling the analog RF signals, a FIR filter for filtering the digitized signals, a re-sampler for re-sampling the digitized signals, and an automatic gain control circuit. This patent application is focused on an automatic gain control function which controls the resampling of the first plurality of bits to form the second plurality of bits in accordance with an automatic gain control signal.
According above discussions, it need a method and apparatus to overcome the disadvantage of the prior art.